Reduction in standby power consumption is an important issue for semiconductor circuits used in portable devices and the like. In order to reduce standby power consumed by semiconductor circuits, power to the semiconductor circuits may be partially cut off using switches provided for the semiconductor circuits when the semiconductor circuits are not in use. Such a mode of reducing standby power consumption by cutting power to the circuits that are not in use for a predetermined period of time is called, for example, a low power mode as distinguished from a normal operation mode.
In the low power mode, memory information in memory macros (semiconductor storages) such as static random access memories (SRAMs) is destroyed when power to memory arrays is cut off. To avoid this, power to peripheral circuits such as predecoders and word line drivers or power to bit lines connected to memory cells is cut off so that standby power consumption is reduced.
In some technologies, power consumed by memory macros such as SRAMs is reduced by controlling bit lines in columns to be precharged or timing of precharging bit lines while memory cell arrays are accessed. In addition, memory cell arrays are divided into a plurality of blocks in order to increase operating speed of memory macros such as SRAMs (see, for example, Japanese aid-open Patent Publication Nos. 01-09816, 02-148497, and 2001-319479).
Herein, memory macros that may operate in a low power mode, in which power to bit lines connected to memory cell of memory cell arrays is cut so that the bit lines are left floating, may have a problem as described below.
For example, when memory macros, switch from a low power mode to a normal operation mode in which memory cell arrays are accessible, all bit lines that have been left floating are reconnected to a power source and precharged on the basis of control signals that control the mode transition. At this moment, however, a relatively high current may flow into the memory macros, and a voltage drop may occur in the entire chip including the memory macros since all bit lines are simultaneously reconnected to the power source. In this case, memory information held in the memory macros may be destroyed.
This problem may become more serious as the capacity of memory macros included in chips increases.